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Morten Zilmer's user avatar
Morten Zilmer's user avatar
Morten Zilmer's user avatar
Morten Zilmer
  • Member for 12 years
  • Last seen more than a week ago
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Electronics engineer engaged in Ethernet network equipment development using FPGA/ASIC and related technologies.

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Top posts
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38
Difference between mod and rem operators in VHDL?
Sep 15, 2014
33
How to convert 8 bits to 16 bits in VHDL?
Jul 3, 2013
26
Reading the PDF properties/metadata in Python
Oct 8, 2016
23
VHDL - How should I create a clock in a testbench?
Jul 29, 2013
22
Wait until <signal>=1 never true in VHDL simulation
Dec 10, 2013
20
Multiplication of two different bit numbers in VHDL
Feb 28, 2015
18
Compile Date and Time in FPGA
Aug 9, 2013
13
Continuous assignment seemingly not working
Aug 15, 2013
12
VHDL Gated Clock how to avoid
Apr 16, 2015
12
Lightweight VHDL simulator in Windows
Aug 15, 2014
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Show attached images in bigger resolution when we click on it
Top network posts
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28
How to get total running time of a hard disk
28
What is sufficient mating material?
18
How to get total running time of a hard disk
14
What are some checkmates with very few moves from the starting position?