Multiple-Block Ahead Branch Predictors - Seznec, Jourdan, Sainrat, Michaud (ResearchIndex)

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Multiple-Block Ahead Branch Predictors (1996) (Make Corrections) (40 citations)
Andr� Seznec, St�phan Jourdan, Pascal Sainrat, Pierre MichaudArchitectural Support for Programming Languages and Operating Systems

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Abstract: : A basic rule in computer architecture is that a processor cannot execute an application faster than it fetches its instructions. To overcome the instruction fetch bottleneck shown in wide-dispatch "brainiac" processors, this paper presents a novel cost-effective mechanism called the multiple-block ahead branch predictor that predicts in an efficient way addresses of multiple basic blocks in a single cycle. Moreover and unlike the previous multiple predictor schemes, the multiple-block ahead... (Update)

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BibTeX entry: (Update)

A. Seznec, S. Jourdan, P. Sainrat, and P. Michaud. Multipleblock ahead branch predictors. In Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems, 1996. To appear. http://citeseer.ist.psu.edu/seznec96multipleblock.html More

@inproceedings{ seznec96multipleblock,
    author = "Andre Seznec and Stephan Jourdan and Pascal Sainrat and Pierre Michaud",
    title = "Multiple-Block Ahead Branch Predictors",
    booktitle = "Architectural Support for Programming Languages and Operating Systems",
    pages = "116-127",
    year = "1996",
    url = "citeseer.ist.psu.edu/seznec96multipleblock.html" }

Citations (may not include all citations):
241 A Study of Branch Prediction Strategies (context) - Smith - 1981
193 Superscalar Microprocessor Design (context) - Johnson - 1991
164 The superblock: An effective technique for VLIW and supersca.. (context) - Hwu - 1993
93 Optimization of Instruction Fetch Mechanisms for High Issue .. - Conte, Menezes et al. - 1995
75 Increasing the Instruction Fetch Rate via Multiple Branch Pr.. - Yeh, Marr et al. - 1993
57 Implementation of Precise Interrupts in Pipelined Processors - Smith, Pleszkun - 1985
46 Tracing with Pixie (context) - Smith - 1991
36 Control Flow Prediction with Tree-Like Subgraphs for Supersc.. (context) - Dutta, Franklin - 1995
33 Intel's P6 Uses Decoupled Superscalar Design (context) - Gwennap - 1995
30 Checkpoint Repair for Out-of-Order Execution Machines (context) - Hwu, Patt - 1987
29 Next Cache Line and Set Prediction - Calder, Grunwald - 1995
26 Two-Level Adaptive Branch Prediction and Instruction Fetch M.. (context) - Yeh - 1993
22 An Investigation of the Performance of Various Dynamic Sched.. (context) - Butler, Patt - 1992
16 Exploring Configurations of Functional Units in an Out-of-Or.. - Jourdan, Sainrat et al. - 1995
9 PA-8000 Combines Complexity and Speed (context) - Gwennap - 1994
9 R10000 Microprocessor Product Overview (context) - Incorporated - 1994
8 Digital Leads the Pack with 21164 (context) - Gwennap
8 Control Flow Prediction for Dynamic ILP Processors (context) - Pnevmatikatos, Franklin et al. - 1993
7 Implementation Trade-offs in Using a Restricted Data Flow Ar.. (context) - Simone - 1995
5 An Investigation of the Performance of Various Instruction-I.. - Jourdan, Sainrat et al. - 1995
4 PowerPC 604 RISC Microprocessor User's Manual (context) - Motorola - 1994
4 Comparing RISC Microprocessors (context) - Gwennap - 1994
3 Architecture and Implementation (context) - Weiss, Smith et al. - 1994
3 PowerPC 620 RISC Microprocessor Technical Summary (context) - Motorola - 1994
3 Don't use the page number, but a pointer to it - Seznec - 1996
1 Combing Branch Predictors (context) - McFarling - 1993
1 Characterizing the Impact of Predicted Execution on Branch P.. (context) - Mahlke - 1994

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