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Reconsidering Complex Branch Predictors (2003)  (Make Corrections)  (3 citations)
Daniel A. Jimenez



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Abstract: To sustain instruction throughput rates in more aggressively clocked microarchitectures, microarchitects have incorporated larger and more complex branch predictors into their designs, taking advantage of the increasing numbers of transistors available on a chip. Unfortunately, because of penalties associated with their implementations, the extra accuracy provided by many branch predictors does not produce a proportionate increase in performance. Specifically, we show that the techniques used... (Update)

Context of citations to this paper:   More

...one block ahead instruction block address. This allows to pipeline the instruction address generator on two cycles. Recently Jimenez [6] showed that ahead pipelining a simple gshare branch predictor may result in a higher fetch bandwidth than using one cycle ahead complex...

Cited by:   More
Piecewise Linear Branch Prediction - Daniel Jimenez Department   (Correct)
Unknown - Institut De Recherche   (Correct)
Effective Ahead Pipelining of Instruction Block Address.. - Andre Seznec And (2003)   (Correct)

Active bibliography (related documents):   More   All
0.6:   Delay-Sensitive Branch Predictors for Future Technologies - Jimenez (2002)   (Correct)
0.3:   Combining Hyperblocks and Exit Prediction to.. - Ranganathan.. (2002)   (Correct)
0.3:   The Impact of Delay on the Design of Branch Predictors - Jiménez, Keckler, Lin (2000)   (Correct)

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Similar documents based on text:   More   All
0.6:   Applying Decay Strategies to Branch Predictors for .. - Hu, Juang.. (2002)   (Correct)
0.5:   Branch Path Re-Aliasing - Jimenez, Lin   (Correct)
0.5:   Alternative Implementations of Hybrid Branch Predictors - Po-Yung Chang (1995)   (Correct)

Related documents from co-citation:   More   All
2:   Neural methods for dynamic branch prediction - Jimenez, Lin - 2002
2:   Design tradeoffs for the ev8 branch predictor (context) - Seznec, Felix et al. - 2002
2:   The impact of delay on the design of branch predictors - Jimenez, Keckler et al. - 2000

BibTeX entry:   (Update)

D. Jimenez. Reconsidering complex branch predictors. In Proceedings of the 9th International Symposium on High Perform ance Computer Architecture, 2003. http://citeseer.ist.psu.edu/jimenez03reconsidering.html   More

@misc{ jimenez03reconsidering,
  author = "D. Jimenez",
  title = "Reconsidering complex branch predictors",
  text = "D. Jimenez. Reconsidering complex branch predictors. In Proceedings of
    the 9th International Symposium on High Perform ance Computer Architecture,
    2003.",
  year = "2003",
  url = "citeseer.ist.psu.edu/jimenez03reconsidering.html" }
Citations (may not include all citations):
132   The Alpha 21264 microprocessor (context) - Kessler - 1999  ACM
117   Clock rate versus ipc: The end of the road for conventional .. - Agarwal, Hrishikesh et al. - 2000  DBLP
91   Two-level adaptive branch prediction (context) - Yeh, Patt - 1991
75   Increasing the instruction fetch rate via multiple branch pr.. - Yeh, Marr et al. - 1993  ACM   DBLP
67   The SimpleScalar tool set version - Burger, Austin - 1997
44   Digital Western Research Laboratory (context) - McFarling, predictors et al. - 1993
42   Trading conflict and capacity aliasing in conditional branch.. - Michaud, Seznec et al. - 1997  ACM   DBLP
40   Multiple-block ahead branch predictors - Seznec, Jourdan et al. - 1996  ACM   DBLP
27   The cascaded predictor: Economical and adaptive branch targe.. - Driesen, Holze - 1998  DBLP
25   The impact of delay on the design of branch predictors - Jimenez, Keckler et al. - 2000  ACM   DBLP
20   Speculative updates of local and global branch history: A qu.. - Skadron, Martonosi et al. - 2000
17   Extensions to cacti (context) - Reinman, Jouppi - 1999
12   Design tradeoffs for the Alpha EV8 conditional branch predic.. - Seznec, Felix et al. - 2002  ACM   DBLP
7   Improving Branch Prediction by Understanding Branch Behavior (context) - Evers - 2000  ACM
6   Neural methods for dynamic branch prediction - Jimenez, Lin - 2002  ACM   DBLP
5   The optimal useful logic depth per pipeline stage is approxi.. (context) - Hrishikesh, Jouppi et al. - 2002
5   GHz PA-RISC processor (context) - Tsai - 2001
4   An integrated cache timing (context) - Shivakumar, Jouppi - 2001
1   AMD's hammer microarchitecture preview (context) - de Vries - 2001
1   AMD's next generation microprocessor architecture (context) - Weber - 2001
1   Intel builds world's first one square micron sram cell (context) - Press - 2002

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Just Say No: Benefits of Early Cache Miss Determination - Memik, Reinman.. (2003)   (Correct)
A Statistically Rigorous Approach for Improving Simulation.. - Yi, Lilja, Hawkins (2002)   (Correct)
Dynamic Data Dependence Tracking and its Application to.. - Chen, Dropsho, Albonesi   (Correct)

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