User Peter Cordes - Stack Overflow

102 votes

3 answers

16k views

Why is the loop instruction slow? Couldn't Intel have implemented it efficiently?

asked Mar 2, 2016 at 9:01

76 votes

1 answer

19k views

What happens if you use the 32-bit int 0x80 Linux ABI in 64-bit code?

asked Sep 7, 2017 at 4:20

58 votes

0 answers

2k views

Per-element atomicity of vector load/store and gather/scatter?

asked Sep 2, 2017 at 9:56

53 votes

2 answers

5k views

How exactly do partial registers on Haswell/Skylake perform? Writing AL seems to have a false dependency on RAX, and AH is inconsistent

asked Aug 13, 2017 at 12:05

34 votes

1 answer

5k views

What are the best instruction sequences to generate vector constants on the fly?

asked Jan 29, 2016 at 12:52

23 votes

2 answers

4k views

Does modern PC video hardware support VGA text mode in HW, or does the BIOS emulate it (with System Management Mode)?

asked Apr 30, 2020 at 10:57

19 votes

3 answers

10k views

How to convert a binary integer number to a hex string?

asked Dec 17, 2018 at 22:14

18 votes

2 answers

5k views

In GNU C inline asm, what are the size-override modifiers for xmm/ymm/zmm for a single operand?

asked Dec 25, 2015 at 3:35

17 votes

2 answers

506 views

Does undefined behaviour retroactively mean that earlier visible side-effects aren't guaranteed?

asked Sep 20, 2023 at 21:48

15 votes

1 answer

3k views

Which 2's complement integer operations can be used without zeroing high bits in the inputs, if only the low part of the result is wanted?

asked Dec 20, 2015 at 3:34

15 votes

2 answers

3k views

Vectorizing with unaligned buffers: using VMASKMOVPS: generating a mask from a misalignment count? Or not using that insn at all

asked Dec 16, 2015 at 8:16

12 votes

2 answers

2k views

Are there any modern CPUs where a cached byte store is actually slower than a word store?

asked Jan 16, 2019 at 12:54

12 votes

1 answer

2k views

Is vxorps-zeroing on AMD Jaguar/Bulldozer/Zen faster with xmm registers than ymm?

asked May 1, 2017 at 1:53

11 votes

1 answer

2k views

Symbol name conflicts with new register names in new NASM versions?

asked Aug 25, 2017 at 23:42

11 votes

1 answer

2k views

How to merge a scalar into a vector without the compiler wasting an instruction zeroing upper elements? Design limitation in Intel's intrinsics?

asked Sep 4, 2016 at 15:24

11 votes

1 answer

2k views

x86-32 / x86-64 polyglot machine-code fragment that detects 64bit mode at run-time?

asked Jun 27, 2016 at 21:27

10 votes

1 answer

878 views

Does Skylake need vzeroupper for turbo clocks to recover after a 512-bit instruction that only reads a ZMM register, writing a k mask?

asked Oct 26, 2019 at 6:14

10 votes

2 answers

728 views

Which Intel microarchitecture introduced the ADC reg,0 single-uop special case?

asked Aug 3, 2018 at 2:06

9 votes

1 answer

2k views

Why can't I mmap(MAP_FIXED) the highest virtual page in a 32-bit Linux process on a 64-bit kernel?

asked Dec 8, 2017 at 10:34

8 votes

2 answers

2k views

How does MIPS I handle branching on the previous ALU instruction without stalling?

asked Jun 13, 2019 at 18:25

8 votes

1 answer

990 views

How to force NASM to encode [1 + rax2] as disp32 + index2 instead of disp8 + base + index?

asked Feb 18, 2018 at 3:44

8 votes

1 answer

1k views

Can PTEST be used to test if two registers are both zero or some other condition?

asked Apr 30, 2017 at 23:03

7 votes

1 answer

806 views

Do FP and integer division compete for the same throughput resources on x86 CPUs?

asked Oct 16, 2019 at 21:55

7 votes

1 answer

2k views

How to write an absolute target for a near direct relative call/jmp in MASM

asked Apr 27, 2018 at 8:39

7 votes

1 answer

2k views

GNU C native vectors: how to broadcast a scalar, like x86's _mm_set1_epi16

asked Nov 21, 2016 at 22:48

2 votes

1 answer

439 views

Does a function with instructions before the entry-point label cause problems for anything (linking)?

asked Feb 17, 2016 at 21:48

2 votes

1 answer

650 views

Write x86 asm functions portably (win/linux/osx), without a build-depend on yasm/nasm?

asked Jul 30, 2015 at 21:20

2 votes

2 answers

2k views

PHP form and DB query input validation

asked Jul 6, 2015 at 21:11

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28 Questions

Why is the loop instruction slow? Couldn't Intel have implemented it efficiently?

What happens if you use the 32-bit int 0x80 Linux ABI in 64-bit code?

Per-element atomicity of vector load/store and gather/scatter?

How exactly do partial registers on Haswell/Skylake perform? Writing AL seems to have a false dependency on RAX, and AH is inconsistent

What are the best instruction sequences to generate vector constants on the fly?

Does modern PC video hardware support VGA text mode in HW, or does the BIOS emulate it (with System Management Mode)?

How to convert a binary integer number to a hex string?

In GNU C inline asm, what are the size-override modifiers for xmm/ymm/zmm for a single operand?

Does undefined behaviour retroactively mean that earlier visible side-effects aren't guaranteed?

Which 2's complement integer operations can be used without zeroing high bits in the inputs, if only the low part of the result is wanted?

Vectorizing with unaligned buffers: using VMASKMOVPS: generating a mask from a misalignment count? Or not using that insn at all

Are there any modern CPUs where a cached byte store is actually slower than a word store?

Is vxorps-zeroing on AMD Jaguar/Bulldozer/Zen faster with xmm registers than ymm?

Symbol name conflicts with new register names in new NASM versions?

How to merge a scalar into a vector without the compiler wasting an instruction zeroing upper elements? Design limitation in Intel's intrinsics?

x86-32 / x86-64 polyglot machine-code fragment that detects 64bit mode at run-time?

Does Skylake need vzeroupper for turbo clocks to recover after a 512-bit instruction that only reads a ZMM register, writing a k mask?

Which Intel microarchitecture introduced the ADC reg,0 single-uop special case?

Why can't I mmap(MAP_FIXED) the highest virtual page in a 32-bit Linux process on a 64-bit kernel?

How does MIPS I handle branching on the previous ALU instruction without stalling?

How to force NASM to encode [1 + rax2] as disp32 + index2 instead of disp8 + base + index?

Can PTEST be used to test if two registers are both zero or some other condition?

Do FP and integer division compete for the same throughput resources on x86 CPUs?

How to write an absolute target for a near direct relative call/jmp in MASM

GNU C native vectors: how to broadcast a scalar, like x86's _mm_set1_epi16

Does a function with instructions before the entry-point label cause problems for anything (linking)?

Write x86 asm functions portably (win/linux/osx), without a build-depend on yasm/nasm?

PHP form and DB query input validation