Unanswered Questions
212 questions with no upvoted or accepted answers
7
votes
1
answer
521
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Is there any defined programming model for 'Self-Learning' NPUs?
Qualcomm is creating a Neuromorphic Processing Unit or an NPU called zeroth.
IBM is also working on a brain inspired chip under Synapse program.
Standford's Neurogrid might be a similar example.
...
CommunityBot
- 1
4
votes
0
answers
144
views
Is there a OSI model equivalent for describing the abstract layers present in performing a computation for an operating system?
In describing where a system vulnerability exists, I often find a need for a model that partitions a operating system and its components into abstraction layers. Similar to how the Open Systems ...
D.W.♦
- 167k
3
votes
1
answer
4k
views
Load and Store Data hazard problem in 5-stages pipeline
Hi everyone and first of all thank you for been reading.
I'm a little confused about data hazard dependences when a "Store" instruction is followed by a "Load" instruction.
(Assume that we're working ...
CommunityBot
- 1
3
votes
0
answers
262
views
Is it possible to figure out cache size and associativity using the length of offset, index, tag fields?
I have a question where I am asked to find the size of a cache. I am given the following info:
a) the length of a memory address
b) the number of bits for offset, index, and tag fields.
I know I ...
- 31
3
votes
1
answer
314
views
MIPS limited dual issue
Some of the MIPS processors like 5kc, 5kf have "limited dual issue". Searching online it seems that this means that the processor allows for a dual issue in only some selected cases, but it is not ...
CommunityBot
- 1
2
votes
1
answer
150
views
Measuring Cache Access Time
I want to make a simple C program in order to measure L1, L2 and L3 latencies of my CPU. I know some info about them:
...
CommunityBot
- 1
2
votes
0
answers
25
views
Does exist another models like CARDIAC, LMC and IPC?
I'm working with CARDIAC (Cardboard Illustrative Aid to Computation) that is a model created at Bell Labs in 1968 to explain students how the computers worked with the Von Neumann architecture to ...
2
votes
0
answers
58
views
Belt-based mechanical computers
I've seen a lot of mechanical computers based on gears and rigid rods, but none so far that consequently use belts (not chains) for transmission of information.
Belts allow for easy negation (by ...
2
votes
0
answers
87
views
Von Neumann mixed with Havard in modern CPU?
Modern CPUs (for a very wider range of "modern") use separate data- and instruction-caches. So at the core they (probably) have separate busses for data and instructions. Does that make the &...
- 121
2
votes
1
answer
124
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Why does CLRS refer to the disk parts as pages rather than blocks?
I recently decided to review the B-tree chapter (chapter 18, p 486 in 3ed) in Introduction Algorithms, and found that they call pages what I always referred to as blocks or clusters:
In order to ...
CommunityBot
- 1
2
votes
0
answers
845
views
Difficulty in understanding the concept of operand forward in pipeling and when to use split phase
Given below is a question from $\text{GATE } 2015 \text{ CS}$ paper,
Consider the sequence of machine instruction given below:
\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
- 1,164
2
votes
0
answers
198
views
Confused with an Instruction Cycle question
Here's the question
The content of PC in the basic computer architecture (given below) is 3AF. The content of AC is 7EC3. The content of memory at address 3AF is A32E. The content of memory at ...
- 21
2
votes
0
answers
55
views
Finding the timestamps of processes implementing Lamport's clocks
I have been asked this question, but don't know how to go about answering it.
Three process, which are implementing Lamport's clocks, are running and a lot of events are taking, place including some ...
2
votes
0
answers
90
views
What is "orthogonality" in the context of Instruction Encoding?
What does it mean by "orthogonality" in the context of Instruction Encoding?
Why CISC Architecture is orthogonal while RISC is not?
CommunityBot
- 1
2
votes
0
answers
67
views
Compiler optimization which does an SMT-like optimization in software?
Say I had two functions called one after the other:
...
- 148