Ben Cohen

1. Understanding the SVA Engine Using the Fork-Join Model 2. Reflections on Users’ Experiences with SVA, part 1 3. Understanding Assertion Processing Within a Time Step 4. Reflections on Users’ Experiences with SVA, part 2 5. Understanding and Using Immediate Assertions 6. SVA Package: Dynamic and range delays and repeats 7. SUPPORT LOGIC AND THE always PROPERTY 8. SVA in a UVM Class-based Environment (alt)

9. Arbiter Paper PDF 9. Arbiter SV File 10. Getting started with verification with SystemVerilog 11. Understanding SVA Degeneracy 11. (alt) 12. Leveraging Bing GPT-4 for Design 12. (supplement) 13. Understanding the within Operator 14. Req/Ack Handshake 15. DYNAMIC DATA STRUCTURES IN ASSERTIONS 16. intersect vs others

1. SystemVerilog Assertions Handbook PDF ($55) 1. Paper Edition (USA) 1. Indian Edition 2. VMM PDF 2. VMM Code 3. Real Chip Design and Verification ($3)

4. Component Design by Example (link 1) 4. (link 2) 4. (code) 4. (archive) 5. Using PSL/Sugar with Verilog and VHDL 6. VHDL Coding Styles and Methodologies 7. VHDL Answers to Frequently Asked Questions